The MPC resides in the middle of the peripheral EMU crate and receives trigger primitives from 9 or 8 Trigger Motherboards (designed at UCLA). MPC'2002 selects three best patterns out of 18 (or 16) and transmits them over three optical links to new combined Sector Receiver/Sector Processor board (designed at the University of Florida).

• Firmware revision 05/10/2010 (Based on revision 10/08/2008, but can disable specific TMB inputs by default (after power cycyling and hard reset). In the 10/08/2008 revision all the TMB inputs are enabled by default. Version mi (i=1..9) masks out one TMBi in the peripheral crate. CSR7 and CSR8 are not needed.
  • Configuration mcs and svf files to mask off the TMB1.
  • Configuration mcs and svf files to mask off the TMB2.
  • Configuration mcs and svf files to mask off the TMB3.
  • Configuration mcs and svf files to mask off the TMB4.
  • Configuration mcs and svf files to mask off the TMB5.
  • Configuration mcs and svf files to mask off the TMB6.
  • Configuration mcs and svf files to mask off the TMB7.
  • Configuration mcs and svf files to mask off the TMB8.
  • Configuration mcs and svf files to mask off the TMB9.

  • MPC'2004 Specification. Version 10/08/2008 (Board_ID[5..0] and Link_ID[1..0] added, CSR7 and CSR8 added to mask/unmask individually any LCT from any TMB, sorting scheme was changed to allow zero-quality LCT's with vpf=1 to participate in sorting. New for this version: when the LCT0 and LCT1 from the same TMB have equal "quality" values, the LCT0 will have the precedence over LCT1. All previous versions of firmware implement the opposite scheme, when the LCT1 had a precedence over LCT0)
    • Configuration mcs file for the XC18V04 EPROM. Version 03/25/2011 (same as version 10/08/2008, but compiled with the ISE 10.1.3)
    • Configuration svf file for the XC18V04 EPROM. Version 03/25/2011 (same as version 10/08/2008, but compiled with the ISE 10.1.3)
    • Configuration mcs file for the XC18V04 EPROM. Version 10/08/2008 (compiled with the ISE 6.2.03).
    • Configuration svf file for the XC18V04 EPROM. Version 10/08/2008 (compiled with the ISE 6.2.03).
  • FPGA Release Notes Version 10/08/2008
  • MPC FPGA Description
  • MPC'2004 Specification. Version 02/12/2007 (Board_ID[5..0] and Link_ID[1..0] added, CSR7 and CSR8 added to mask/unmask individually any LCT from any TMB, sorting scheme was changed to allow zero-quality LCT's with vpf=1 to participate in sorting)
    • Configuration mcs file for the XC18V04 EPROM. Version 10/27/2006 (including Board_ID[5..0] and Link_ID[1..0], CSR7 and CSR8, zero-quality LCT's with vpf=1 participate in sorting)
    • Configuration svf file for the XC18V04 EPROM. Version 10/27/2006 includes the  Board_ID[5..0] + Link_ID[1..0], CSR7 and CSR8, zero-quality LCT's with vpf=1 participate in sorting.

  • MPC'2004 Specification. Version 10/26/2006 (Board_ID[5..0] and Link_ID[1..0] added, CSR7 and CSR8 added to mask/unmask individually any LCT from any TMB)
  • Configuration mcs file for the XC18V04 EPROM. Version 10/26/2006 (including Board_ID[5..0] and Link_ID[1..0], CSR7 and CSR8, zero-quality LCT's with vpf=1 do not participate in sorting)
  • Configuration svf file for the XC18V04 EPROM. Version 10/26/2006 (including Board_ID[5..0] and Link_ID[1..0], CSR7 and CSR8, zero-quality LCT's with vpf=1 do not participate in sorting).
  • MPC'2004 Specification. Version 04/26/2006 (Board_ID[5..0] and Link_ID[1..0] added)
  • Configuration mcs file for the XC18V04 EPROM. Version 04/26/2006 (including Board_ID[5..0] and Link_ID[1..0])
  • Configuration svf file for the XC18V04 EPROM. Version 04/26/2006 (including Board_ID[5..0] and Link_ID[1..0]).
  • MPC'2004 Specification. Version 11/24/2005 (Including transparent BC0)
  • Configuration mcs file for the XC18V04 EPROM. Version 11/24/2005 (Including transparent BC0)
  • Configuration svf file for the XC18V04 EPROM. Version 11/24/2005 (Including transparent BC0)
  • Configuration svf file to program XC18V04 EPROM. Version 10/20/2005
  • Configuration svf file to verify XC18V04 EPROM. Version 10/20/2005
  • Configuration mcs file for the XC18V04 EPROM. Version 04/23/2005
  • Configuration svf file to program XC18V04 EPROM. Version 04/23/2005
  • Configuration svf file to verify XC18V04 EPROM. Version 04/23/2005
  • Configuration svf file to erase XC18V04 EPROM. Version 04/23/2005
  • MPC2004 .ucf file
  • Eye diagram and jitter measurements at the SP input (differential outputs DOUTTXP/DOUTTXN of the TLK2501 receiver; 100 m multimode fiber; 1.6Gbps rate)
  • MPC2004 Schematic (pdf files)
    • TLK2501 Transmitters
    • Mezzanine Connectors
    • VME Interface
    • Custom Backplane Interface

  • MPC2004 special project with the LFSR-based 15-bit PRBS generators for the optical links. Identical PRBS generators for all three links. PRBS generators run continuously after power cycling. Links need to be initialized by sending the L1Reset command. The generators are reset by the BC0 pulse which is transmitted as a 16th bit in the datastream from the MPC to SP. Interface to TMBs, sorter unit, FIFO_A and FIFO_B are not available.
    • mcs file for XC18V04 EPROM
    • svf file for the XC18V04 EPROM
    • Simplified block diagram of the transmitter and receiver PRBS logic. BC0 in the transmitter part here is a 12.5 ns pulse derived from the 25 ns BC0 TTC command.

  • Firmware for the MPC2004, version 05/20/2008. Same as 10/27/2006, plus 16-bit L1Reset counter added. Available for read (base address + B4). Reset on "FPGA Soft Reset command.
  • Configuration mcs file for the XC18V04 EPROM. Version 05/20/2008
  • Configuration svf file for the XC18V04 EPROM. Version 05/20/2008.
  • MPC-to-SP Synchronization Procedure (L.Uvarov)
  • MPC2004 Xilinx project (zip) . Version 10/27/2006 (open with Xilinx ISE 6.2.03).
  • MPC2004 Xilinx project (zip) . Version 10/08/2008 (open with Xilinx ISE 6.2.03).
  • Example of IDCODE/USERCODE read procedure via JTAG from XC18V04 EPROM (.txt file)
  • Simplified TMB2005-to-MPC2004 data transmission test code (.txt file)

  MPC'2002 for the EMU Peripheral Electronics (Initial Prototype, April 2002)

  
  • Description of the modified MPC firmware (version 05/30/2004). Supports both "sorter" and "transparent" modes. In a "transparent" mode the MPC may send any incoming LCT (out of 18) to any optical link without sorting.
  • Configuration mcs and svf files for XC18V04 EPROM ("sorter" and "transparent" modes). Version 06/08/2004
  • MPC'2002 Specification. Version 05/28/2003
  • Configuration file for XC18V04 EPROM. Version 11/04/2002
  • Configuration file for XC18V04 EPROM (including Soft_reset, MPC_Soft_Reset, BXReset (cmd[5..0]=32(hex) commands). Version 05/02/2003
  • Configuration file for XC18V04 EPROM (including MPC-to-SP synchronization procedure as of 05/19/03). Version 05/19/2003
  • Configuration file for XC18V04 EPROM (including MPC-to-SP synchronization procedure as of 05/25/03). Version 05/25/2003
  • MPC Schematic (pdf files)
    • TLK2501 Transmitters
    • Mezzanine Connectors
    • VME Interface
    • Custom Backplane Interface
  • MPC Mezzanine Card with XCV600E FPGA (pdf files)
    • Top View
    • Bottom View
    • Schematic
  • Xilinx LogiCore Asynchronous FIFO V3.0 Specification
  • Texas Instruments TLK2501 Gigabit Transceiver Specification
  • Finisar FTRJ-8519-1-2.5 Optical Module datasheet
  • MPC'2002 Backplane connector drawing (.dxf file)

  MPC'2000 for the EMU Peripheral Electronics

  This is the first prototype of MPC designed in 2000. The board is able to receive up to six trigger primitives from three Trigger Motherboards TMB'99, select three best and transmit them to Sector Receiver prototype designed at UCLA in 2000. The boards were used at the University of Florida for joint tests with a prototypes of Sector Receiver and Sector Processor modules.

  

  • MPC'2000 Specification. Version 10/13/2000

  Muon Sorter

  Muon Sorter receives up to 36 reconstructed muon primitives from 12 Sector Processors, selects the four best and transmits them to the Global Muon Trigger crate for further processing. Muon Sorter resides in the middle of the Track Finder crate and communicates with the Clock and Control Board (CCB) and Sector Processors over custom backplane.

  MS2005 (Modified Version, July 2005)

  Board Status (Location, Firmware, Hardware, Mezzanines)

   

  

  • MS2005 Specification. Version 1.5, 09/07/2009
    • Configuration files (.mcs) for XC18V04 EPROM1, EPROM2, EPROM3, EPROM4, version 03/25/2011 (same as version 09/07/2009, but compiled with the ISE 10.1.3).
    • Configuration svf file for all four XC18V04 EPROMs, version 03/25/2011 (same as version 09/07/2009, but compiled with the ISE 10.1.3).
    • Configuration files (.mcs) for XC18V04 EPROM1, EPROM2, EPROM3, EPROM4, version 09/07/2009 (based on version of 03/31/2009 with four "rate" counters added, compiled with the ISE 6.2.03).
    • Configuration svf file for all four XC18V04 EPROMs, version 09/07/2009 (compiled with the ISE 6.2.03).

  • Configuration files (.mcs) for XC18V04 EPROM1, EPROM2, EPROM3, EPROM4, Trial version (based on version of 09/07/2009, compiled with the ISE 6.2.03).
  • Configuration svf file for all four XC18V04 EPROMs, DATE_ID=169Dh (compiled with the ISE 6.2.03).
  • MS2005 Specification. Version 1.4, 03/09/2009
    • Configuration files (.mcs) for XC18V04 EPROM1, EPROM2, EPROM3, EPROM4, version 03/31/2009 (parity calculation for the GMT was changed from XNOR[29:0] to XOR[29:0]; trigger start/stop commands are not needed any more to send the BXN[2:0] bits from the internal bunch crossing counter to the GMT; bit CSR6[15] was specified to allow data capture from sorting unit to FIFO_D).
    • Configuration svf file for all four XC18V04 EPROMs, version 03/31/2009.
  • FPGA Release Notes Version 03/31/2009
  • PLD Release Notes Version 08/16/2005
  • MS FPGA Description
  • MS PLD Description
  • MS2005 Specification. Version 1.3, 06/26/2007
    • Configuration files (.mcs) for XC18V04 EPROM1, EPROM2, EPROM3, EPROM4, version 06/26/2007 (same functionality as version 07/31/2006, but more flexible control of the output RAM).
    • Configuration svf file for all four XC18V04 EPROMs, version 06/26/2007.

  • MS2005 Specification. Version 1.2, 03/01/2007

    • Configuration files (.mcs) for XC18V04 EPROM1, EPROM2, EPROM3, EPROM4, version 07/31/2006 (same functionality as version 11/11/2005, but reduced latency = 125 ns)

    • Configuration files (.mcs) for XC18V04 EPROM1, EPROM2, EPROM3, EPROM4, version 11/11/2005 (latency = 150 ns)

    • Erase EPROM's svf file for all four XC18V04 EPROMs, version 11/11/2005
    • Configuration svf file for all four XC18V04 EPROMs, version 07/31/2006
    • Configuration svf file for all four XC18V04 EPROMs, version 11/11/2005
    • Configuration svf file for all four XC18V04 EPROMs, version 08/16/2005
    • Configuration evf file for all four XC18V04 EPROMs, version 08/16/2005
    • Programming jed file for Xilinx XCR3128XL PLD, version 08/17/2005
    • Programming jed file for Xilinx XCR3128XL PLD, version 07/29/2003
    • Programming jed file for Xilinx XCR3128XL PLD, version 11/05/2003

  • MS2005 LUT dump (version October 2009)
  • MS2005 LUT dump (version October 2007)

• MS2005 Schematic (pdf files)
  • Custom backplane interface
  • VME interface
  • FPGA mezzanine connectors
  • Interface to Global Muon Trigger

• Specification of the MS-to-GMT non-halogen copper cable
• MS2005 Xilinx FPGA project (zip) . Version 09/07/2009 (open with Xilinx ISE 6.2.03).
• MS2005 Xilinx FPGA project (zip) . Version 03/31/2009 (open with Xilinx ISE 6.2.03).
• MS2005 Xilinx FPGA project (zip) . Version 06/26/2007 (open with Xilinx ISE 6.2.03).
• MS2005 Xilinx PLD project (zip) . Version 08/16/2005 (open with Xilinx ISE 6.2.03).

MS2003 (First Version, February 2003)



• Muon Sorter Specification. Version 2.1, 11/19/2004 (with four output RAM buffers)
  • Configuration files (.mcs) for XC18V04 EPROM1, EPROM2, EPROM3, EPROM4, version 12/02/2004
  • Configuration (evf) file for all four XC18V04 EPROMs, version 12/02/2004
• Muon Sorter Specification. Version 2.0, 05/04/2004
  • Configuration files (.mcs) for XC18V04 EPROM1, EPROM2, EPROM3, EPROM4, version 06/16/2004 (modified data format to GMT, modified "winner" bits to SP)
  • Configuration files (.svf) for XC18V04 all 4 EPROM's, EPROM1, EPROM2, EPROM3, EPROM4, version 06/16/2004
  • Configuration files (.mcs) for XC18V04 EPROM1, EPROM2, EPROM3, EPROM4, version 12/10/2003
• MS Schematic (pdf files)
  • Custom backplane interface
  • VME interface
  • FPGA mezzanine connectors
  • Interface to Global Muon Trigger
• EPROM Configuration file (.evf) for SCANPSC100F controller, version 12/10/2003
• Configuration file (.jed) for XCR3128XL PLD, version 11/05/2003
• National SCANPSC100FSC JTAG Controller
• Mechanical Drawing of the backplane connectors, 12/06/2002
• CSC Track Finder Crate Specification. December 2002.
• Specification if the Interface Between the Regional Muon Triggers and the Global Muon Trigger. CMS Internal Note IN 2004/022 Version 1.00. June 8, 2004