Jay Hauser, Mike Matveev and B.Paul Padley

UCLA, Los Angeles, CA and Rice University, Houston, TX

04/24/1998

This is a preliminary design report documenting our initial design ideas for the the Sector Receiver Card (SRC) of CMS Endcap Muon (EMU) System.

The Endcap Muon System at the CMS experiment includes four stations of CSCs. The chambers serve two purposes: muon track reconstruction and triggering. Each muon chamber subtends either 10 or 20 degrees of azimuth and consists of six layers of CSCs. The CSCs in turn have cathode strips running in the radial direction and anode wires perpendicular to the strips. Together, strip and wire data from the CSCs allow reconstruction of a three-dimensional muon track stub. Strip and wire Local Charged Tracks (LCT) are processed by strip and wire Front End Boards (FEB). Every 25ns each FEB can send one selected LCT to the Motherboard (one per chamber) via serial copper link. Each Motherboard consists of two parts: the Trigger Motherboard (TMB) and the Data Acquisition Motherboard (DAQMB). Up to seven wire and up to five strip FEBs may be connected to one TMB. All FEBs and MBs are mounted on chamber. The TMB is responsible for the reduction of the number of LCTs coming from FEBs (based on data content), data transmission to the MPC and DAQMB and also for signals distribution from Timing, Trigger and Control System (TTC). The DAQMB is responsible for data acquisition from FEBs.

Each TMB selects the two best LCTs out of 12 possible and sends them to the MPC via serial copper links. Each MPC receives signals from 9 chambers in one station. In stations 2, 3 and 4 this corresponds to 60 degrees while in station 1 this corresponds to 30 degrees. Each MPC reduces the number of LCTs to, at most, three and sends them to SRC via optical links. Each SRC receives data from two Muon Stations ME and performs data conversion (optical to copper and serial to parallel), its alignment and reformatting. The reformatted data is sent from the SRC to Sector Processors (SP). SRC and SP cards will be located in a VME crates in the counting room. Sector Processors perform track reconstruction and sending data to Global Muon Trigger System. The general block diagram of CSC Trigger Electronics is given on Fig.1. The numbers of boards, links and crates are given in Table 1 including the option where only three CSC stations are initially built.

Table 1

Number of boards, crates and links for the CSC Muon Trigger System

The SRC performs the following functions:

• Every bunch crossing (25 ns) the SRC receives LCTs from two MPC via optical links, up to three LCTs per MPC , each LCT contains 46 bits of data

• Synchronization of incoming LCTs with the SRC local master clock

• Communication with the Track Finder in overlap region

• Translation of strip and wire patterns into positions, rapidity and angles via Look-Up Tables

• Alignment correction to the track positions

• Communication with the SP

• VME Slave functions

Figure 1: A block diagram of the Sector Receiver Card

The data bits per one muon stub sent from MPC to SRC are listed in Table 2. The main requirement of MPC-SRC links is to transmit three LCTs, or 46*3=138 bits every 25ns, so the total required bandwidth is about 5.5Gbit/s. The distance between on-chamber electronics (FEBs, MBs, MPC) and the counting room is about 100m, so the only acceptable method of data transmission is optical.

Table 2

LCT content (from each MPC to SRC)

Data comes from the MPCs to SRCs via optical fibers, so each MPC should contain parallel to serial converters and optical transmitter modules, and each SRC should contain a number of optical receiver modules and serial to parallel converters. A list of chipsets (receiver and transmitter, or integral transceiver) available from different companies for Gbit optical links, and some available optical modules are discussed in more details in the MPC specification.

Two options in the design and development of optical links seem the most promising for our application. The first one is a custom design. One example is the MATCH serialiser [1] developed at INFN. It is a fully asynchronous electrical parallel-to-serial and serial-to-parallel transceiver using Manchester encoding operating at rates of up to 1 GHz. Data are sent as 40 bit frames with 32 bit net data, the chip protocol is fully asynchronous. There is error detection. The chip itself foresees no flow control. The chip is implemented in GaAs and its radiation hardness is several Mrad.

Paper [2] proposed a development at CERN/ECP of the custom LHC-oriented Gigabit optical link based on CMOS Deep-Submicron technology available now. The advantages of this design are:

• convenient user interface (input/output 8/16/24 bit bus interface, input strobe and 3 input frequencies, output sync signal and error indicator)
• no coding necessary (done inside)
• very good radiation hardness (at least several Mrad)
• low power dissipation (0.04uW/gate*MHz)
• high level of integration and low cost.

Unfortunately, the future and perspectives of these projects are not clear now.

Progress in optical technology may allow us to use the second option, multichannel optical modules.

Samples of four-channel (1.25Gbit/s per channel) optical receiver and transmitter modules were developed, for example, in 1996 by Vixel Corp [3], but they are not available currently.

Hewlett Packard recently announced a ten-channel parallel optical link module, POLO-2, operating at 1Gbit/s per channel developed in the POLO (Parallel Optical Link Organization) program [4]. This transceiver module provides a data transmission up to 300m over 10 fibers at 1Gbit/s baud rate per channel. Power dissipation is <2W, or <0.1W/channel. The transmitter input and receiver output interfaces are differential ECL. The optical module and transceiver IC are packaged in a 324-pin ceramic BGA package. A multichannel ribbon fiber cable provides much higher density in comparison with single fibers, low attenuation and skew, competitive cable cost and future scalability to multi-Gbit line rates. Only one POLO-2 module can provide complete optical connection between SRC and MPC. The final module specification is not published yet and price is unknown.

Siemens and Motorola Optical Divisions also plan to develop parallel optical links (PAROLI and OPTOBUS projects respectively). According to Motorola, Optobus I MC94DL0400 Multichannel Optical Data Transceiver and Optobus II PC94DL0800 Optical Multichannel Data Link will be available in 4Q97 and 2Q98 respectively.

We intend to continue studying of the complete optical link solutions and will use the results and experience gained by other CMS groups.

Signals from all CSC stations come into the SRC in CSC-only Track Finder crates. This information is needed at the same time in overlap region Track Processor crates. So each MPC should send selected LCTs to both CSC-only and CSC/DT overlap Track Finders.

One solution is to double the number of optical links from the MPC to the SRC (48 instead of 24 in case of three CSC stations) and optical transmitters (presumably, 336 instead of 168 single-channel transmitters) on the MPCs and send the same data from one MPC to two SRCs. In this case all SRCs will contain only optical receiver logic despite their location (CSC-only or CSC/DT overlap crates). Another solution is to send data from the MPC only to SRC in the CSC-only crate, but this SRC will then retransmit this data to its "mirror" SRC in CSC/DT overlap crate. The first solution is more expensive and will complicate the MPC design. The second solution is less expensive and doesn’t affect the design of MPC. There are two possible options: a transmission between two SRCs either via optical or copper cable. In the first case 14 optical repeaters are needed on each SRC. In the second case each SRC should contain a set of high speed serial copper link transmitters and receivers.

One possible candidate for the transmission via copper link is a National Semiconductor LVDS Channel Link DS90CR283/284 chip set. 138 bits of data (three incoming LCTs) on the outputs of serial-to-parallel converters serve as inputs for these Channel Links. The DS90CR283 transmitter converts 28-bit parallel word into four data streams and one clock stream, and the receiver DS90CR284 converts these streams into parallel data and corresponding strobe signal. In order to transmit/receive 138 bits of data we need five Channel Link transmitters and five receivers on each SRC. 20 signal pairs are necessary for data communication between two SRC.

Vitesse VSC7214 Quad Backplane Interconnect Chip (160-pin OQFP package, +3.3V Supply, 4.8W power consumption) contains four 8B/10B encoders, serializers, deserializers and elastic buffers operating at a maximum data rate of 960Mbit/s (120MHz) each. Five VSC7214 chips and 20 signal pairs are necessary for communication between two SRC.

When the LCTs are sent from the MPC to the SRC they might have a constant shift in phase with respect to the local clock at the destination. We will follow the general rule proposed in [5]: synchronize the phase of the signal at the destination to the local clock. We assume that the SRC will receive a 40.08 MHz clock via the backplane from the Clock Control Board (CCB) located in the same VME crate as the SRC and the SP. We also assume that optical receiver module (or serial-to-parallel converter after the optical module) will provide the strobe signals necessary to strobe the incoming LCTs into SRC input logic. For the synchronization we propose to use a pipeline shift registers on the inputs of LCT logic. The synchronization is ensured by delaying the data coming faster than others. These delays are programmable and will be set up after the counting of the time of flight, detector response, and all logic and cable delays.

138 bits represent three LCTs coming into SRC input logic after serial-to-parallel conversion. This logic performs the synchronization of input data with the SRC local master clock , and its outputs serve as addresses for the data conversion logic based on Look-Up Tables.

The SRC translates strip and wire LCTs into parameters more convenient for further processing in the SP: muon track positions, rapidity, local bend angle, and some quality bits. The phi position and local bend angle of the track are based on the 18-bit cathode LCT tag and 4-bit chamber ID. The rapidity is based on the wire 14-bit LCT tag and 4-bit chamber ID. As shown in [6] the required precision of the track position within a 60 degree sector is 12 bits for phi position, 6 bits for local bend angle, and 11 bits for rapidity. As in the Barrel DT detector, there are an additional three quality bits, which will be defined later. Look-Up Table (LUT) RAMs can do this translation for each selected LCT. The position and angle logic require 18 + 4 = 22 to 12 + 6 = 18 bit conversion, or 4M*18 bit LUT RAM, and rapidity logic requires 14 + 4 = 18 to 11 bit conversion, or 256K*11 LUT RAM.

Typically the CSC chambers are to be placed with 2-3mm accuracy [7], whereas the required trigger momentum resolution demands 300um resolution on each track segment. So six numbers (three for position and three for rotation angles) per chamber are needed to correct the chamber positions relative to global system. The same corrections are applied to every track segment, regardless of position within a chamber or angle.

These corrections may be done using the LUTs discussed above.

LUT logic may be realized using existing high-speed 256K*16 or 512K*8 static RAMs (for example, Hitachi 256K*16 bit TC55V16256; 12..20ns access time, 3.3V power supply, SOJ44 package, 190mA/package, or Motorola 256K*16 bit MCM6343; 10..15ns access time, 3.3V power supply, SOJ44 package, 230mA/package, or Motorola 512K*8 bit MCM6946; 10..15ns access time, 3.3V power supply, SOJ36, 180mA/package).

The number of bits which need to be send from one SRC to SP is 32bit/LCT*3LCT=96 in the CSC system (Table 6).

Table 6

The scheme proposed in [6] for a CSC-only Track Finder comprises three groups of modules, each with two SRCs and one SP. This way one needs 96*2=192 signal lines only for data, and one ground line per approximately eight signal lines, total 192+24=216 lines. And this is a minimal requirement, because some additional lines (clock, control…) are also needed. One possible solution the use of a high-density Z-pack 2mm connector [8] (available from AMP and used for Futurebus+ applications). The number of positions (4 rows per connector) may be 192, 216, 240, or 264. There are about 263mm free space vertically in a 9U Eurocrate available for the custom backplane below the standard VME J1 connector. The length of 240-pin connector is about 120mm, so any two connectors with 240 positions or less (and possibly, a 264-pin connector as well) may be located vertically on a custom backplane.

Another solution is the use of AMP Z-pack Stripline 100 connectors [9], available in sizes of 120 through 820 positions.

We could also possibly take advantages of the new 160-pin 5-row VME connector (64 extra lines excepting standard VME signals).

The use of high-speed serial links for point-to-point backplane connections is an alternative to parallel data transmission. For example, using the National Channel Link DC90CR283/284 chip set one can convert 28 parallel bits into 5 serial streams (four data streams and one clock stream) and transfer them via a custom backplane from each SRC to SP. In order to transmit 92 bits of data from SRC to SP after reformatting we need four Channel Link Transmitters on each SRC and eight on each SP. The total number of signal pairs (because signals are differential) is 5 (4 data + 1 clock streams per Channel Link) * 4 (Channel Links per SRC) * 2 (SRC) = 40.

Nine Motorola Autobahn transceivers operating at 200Mbyte/s may realize the same communication path using only nine differential signal pairs.

The full list of signal lines between SRC and SP, as well as data exchange protocol, connectors and backplane will be specified later, upon progress in SRC and SP design.

The VME Interface performs the Slave functions and provides:

• control and monitoring of optical receivers
• testing of data paths between MPC and SRC, and between SRC and SP

• LUT RAMs downloading and testing

Our preliminary estimation of the SRC latency are summarized in Table 7.

Table 7

SRC Latencies

We propose to build a SRC as a VME 9U board (presumably 400mm depth). SRC will receive all optical signals via front panel and communicate with SP via custom backplane located below standard VME backplane.

[2] J.Christiansen et al. Proposal for a Gigabit Link for LHC. CMS Workshop on Optical Links. CERN, 01/16/1998.

[3] Computer Design, July/1996, p.160.

[4] Hewlett Packard Journal. December 1997. See www2.hp.com/hpj/97dec/de97a6.htm

[5] Grzegorz Wrochna. Muon Detector Synchronization. Data Acquisition Workshop. CERN, 11-12.02.1998. http://cmsdoc.cern.ch/~wrochna/mutrig/musynch2.ps

[7] Jay Hauser. Baseline Design for the CSC-based Endcap Muon Trigger. CMS TN95-013. Version 2.6, July 24, 1996.

[8] AMP Interconnection Systems Selection Guide. Catalog 82750. Revised 7-95. Pp.3363..3372.

[9] AMP Interconnection Systems Selection Guide. Catalog 82750. Revised 7-95. Pp.3352..3362.

Fig.1. Sector Receiver Block Diagram